1. Field of the Invention
The present invention relates to integrated circuits. More particularly, the present invention relates to apparatus and methods for reducing leakage in unused ones of the buffers employed for making interconnections in integrated circuits such as field programmable gate arrays (FPGAs) and other programmable logic devices (PLDs).
2. The Prior Art
Configurable integrated circuits such as FPGAs and other programmable logic devices require numerous inverting or non-inverting buffers to implement interconnections. Because the buffers may drive substantial capacitive loads in some cases, they are usually designed using relatively large transistors. FPGA routing typically consists of a multiplexer whose select inputs are set at configuration time and a buffer driven by the output of the multiplexer. Most multiplexer inputs are driven by ordinary variable logic signals. An additional input may be present to force an unused buffer into a known fixed state; this is done by providing a way to “tie off” the input of an unused buffer to either 0V or VCC.
With submicron VLSI processes, leakage current through the large transistors used in the interconnection buffers can be substantial even when they are turned off. This wastes power.
Various techniques have been proposed to reduce leakage of used or unused buffers in FPGAs, including altering the bias of the wells containing the buffer transistors, and selective use of transistors with different threshold voltages. Other methods have also been proposed.